Electromagnetic Wave Group - Advanced Microwave and RF-SOP Technology

A record-high 60-GHz CMOS power amplifier is successfully demonstrated with the state-of-the-art +18dBm output power in 90nm CMOS technology [1]. A fully integrated millimeter-wave (MMW) distributed active transformer (DAT) is ed as the four-way power combination topology to provide a broadband gain performance of 26dB (+/- 1.5dB) from 55 to 71 GHz, which covers a world-wide full-band for 60-GHz WLAN/WPAN applications, i.e. 57-66GHz.

A 20–24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18μm standard CMOS process [2]. By cascading two cascode stages, this PA achieves 16.8 dBm output saturation power with a high power density per chip area of 0.137 W/mm2, which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35mm2, which is the smallest one compared to all reported papers.

A W-band CMOS power amplifier is demonstrated in 90nm CMOS technology [3]. By utilizing balanced architecture, the PA achieves a maximum small signal gain of 17 dB with 3 dB bandwidth from 91 to 108 GHz. The PA features a saturation output power (Psat) of 12 dBm between 90 and 100 GHz, which is the highest frequency CMOS PA reported to date.

Another fully integrated 24-GHz 22-dBm power amplifier was designed and fabricated in 0.18-μm CMOS technology [4].  Optimized device size selection and resonance matching techniques are adopted in this single stage power amplifier design. 

A power amplifier use resistive feed-back and transformer matching network design to enhance the broadband frequency response [5]. The broad-band load impedance match is realized using series stack topology. The limitation of stack PA in both GaAs and CMOS processes are discussed. A high-efficiency broadband PA in commercial 0.18 μm CMOS process with the best P_1dB of 20 dBm and PAE of 30% are demonstrated to verify the design concepts.

A K-band power amplifier that dynamically adjusts the dc consumption based on the output power is implemented [6].  Compared with a fixed-bias PA that consumes a constant dc power of 265 mW, the proposed PA saves 157 mW at quiescent state and 88 mW when operating at P_1dB of 6-dB back-off, and the OP_1dB of the PA is also extended. This is the first CMOS PA with effective enhancement in back-off efficiency near MMW region.

A novel method to generate an auxiliary third-order intermodulation (IM3) signal can be used in the linearization of power amplifiers (PAs) by canceling the output IM3 power [7]. This auxiliary signal is simply achieved by exploiting the input reflected power of the main device, rather than being obtained by conventional methods as driving a highly non-linear device or subtracting the fundamental power from the output signal. It is demonstrated that substantial IM3 power can be reflected to the source with little reflected fundamental power under some input matching conditions of the device, and this feature can be utilized in the design of monolithic microwave integrated circuits (MMICs) targeting excellent linearity. A 25-GHz pHEMT power amplifier is designed and fabricated to exemplify the proposed technique. With the linearization, the OIP3 of the proposed PA increases by 14 dB from 25 to 39 dBm, and the output power enhances significantly, from 5 to 14 dBm with -40-dBc IM3 distortion and from 9 to 14 dBm with -40-dBc adjacent channel power ratio.

A compact and broadband 0.8–77.5-GHz passive distributed down-converter using standard 0.13-μm CMOS technology is implemented [1]. This converter consumes zero dc power and exhibits a measured conversion loss of 5.5dB (+/-1 dB) from 0.8 to 77.5 GHz with a compact size of 0.67mm x 0.58 mm. The output 1-dB compression point is 8.5 dBm at 20 GHz. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This single-chip converter can be used to convert multi-band and multi-standard signals, including cellular, WiFi/WiMAX, GPS, satellite communications, 60-GHz WLAN/WPAN, and automotive radars. To best of our knowledge, this down-converter has the widest operation bandwidth, 76.7 GHz, among all reported CMOS wideband converters to date.

A 30–100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer is fabricated using 90 nm standard CMOS technology [2]. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed trans-conductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits 1.5+/-1.5 dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm2. The OP1 dB of the mixer is 10.4 dBm and 9.6 dBm at 77 and 94 GHz, respectively. This monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.

A new ring-based triple-push voltage-controlled oscillator (VCO) architecture to achieve a state-of-the-art wide tuning range and high operation frequency is demonstrated [3]. Two VCOs with continuous frequency tuning range of 0.2-34 GHz and 0.1-65.8 GHz without any device-switching operations are fabricated in CMOS 0.13-μm and 90-nm technology. The small chip areas including testing pads are 0.095 mm2 and 0.017 mm2, allowing integration into a phase-locked loop. Over the operation frequencies, the fundamental and second harmonic rejections are all better than 15 dB.

 A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented in [1] for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power amplifier (PA) achieves a Psat of 10.72 dBm and OP1dB of 7.3 dBm from 1.2 V supply. After linearization, the OP1dB has been doubled from 7.3 to 10.2 dBm and the operating PAE at OP1dB consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.

A K-band power amplifier that dynamically adjusts the dc consumption based on the output power is presented in [2]. Compared with a fixed-bias PA that consumes a constant dc power of 265 mW, the proposed PA saves 157 mW at quiescent state and 88 mW when operating at P1dB 6-dB back-off, and the OP1dB of the PA is also extended. This is the first CMOS PA with effective enhancement in back-off efficiency near MMW region.

To improve the linearity of the cascode amplification cell while maintaining reasonable gain, a new technique, called splitting cascode, is proposed in [3]. The measurement results show an improvement in the IM3 distortion level of more than 20 dB from 54 to 66 GHz.

The cellular phones that support multiple communication standards such as Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), and Wideband Code Division Multiple Access (WCDMA) require different power amplifier (PA) modules for each standard. The current GSM/EDGE combo PA module enabled dual-standard operation, but at the expense of low EDGE mode efficiency to meet linearity requirements. The stringent linearity requirement of EDGE results from the use of a non-constant envelope modulation unlike the constant-envelope modulation used in GSM. In recent years, WCDMA has started to gain popularity because of the need of higher data rate transmission. The WCDMA standard also uses a non-constant envelope modulation similar to EDGE, but with a much wider bandwidth, which leads to yet another PA if WCDMA standard is to be supported by the cellular phone.

To reduce the overall cost of multi-mode cellular phones, it is highly desirable to have PAs that support multiple communication standards while maintaining high efficiency at the same time. Digital pre-distortion for the linear PAs that supported EDGE and WCDMA was successfully demonstrated. However, pre-distortion normally leads to increased power consumption and circuit complexity while suffering from the inherent low efficiency of linear PAs. The envelope elimination and restoration (EER) technique proposed by Kahn is capable of high-efficiency linear amplification. Its adaptations for highly efficient multi-mode PAs have been demonstrated, but requiring the use of feedback, digital pre-distortion, or calibration. Moreover, the separation of the phase and the envelope signals in the EER technique required accurate synchronization to avoid unwanted out-of-band emission. The envelope-tracking (ET) technique has potential for multi-mode operation, but requiring wide bandwidth supply circuits as in EER and has lower efficiency because of the use of linear PAs.

The pulse-modulated polar transmitter (PMPT) technique was proposed and developed. By using interleaving pulse-width modulation (PWM) with a well-chosen PWM sampling frequency for GSM/EDGE/WCDMA multi-mode cellular applications, the spurs are kept from falling into the receive bands. Through interleaving pulse modulation, the odd harmonics of the inherent pulse spurs can be cancelled to ease the filtering requirements for signal restoration. A prototype system was constructed and evaluated. The measurement results show that the proposed PMPT can attain excellent power-added efficiency (PAE) for all supported standards at peak power and under back off while meeting spectral requirements. In addition, the PMPT can achieve an output power dynamic range of 80 dB using the CDMA/WCDMA standard.

VCOs are the most important and power-hungry components of the high-frequency signal sources for the wireless communication systems. In order to achieve high-level integration of the transceiver, CMOS VCOs have attracted great attention. However, due to the high-loss substrate and the inherently high flicker noise of the MOSFETs, to design a high-frequency CMOS with good phase noise under low dc power consumption is still a challenge for circuit designers. Transformer-feedback topology is a candidate to implement a low-power and low-noise VCO due to the better quality factor and relaxing voltage swing. We have designed three transformer-feedback CMOS VCOs with low noise characteristics under low dc power consumption.

An ultra-low-power VCO based on the complementary cross-coupled structure with the three-coil transformer feedback is proposed and realized in 0.18 μm CMOS [1]. This VCO has a 1 MHz offset phase noise of -118.5 dBc/Hz under 0.66-mW dc consumption, and the FOM is -198.6 dBc/Hz at 8.2 GHz.

A modified Colpitts VCO is proppsed by replacing the timed current switches of the conventional Colpitts VCO with a differential transformer, and thus the supply voltage of the proposed VCO can be reduced [2]. The VCO implemented by 0.13μm CMOS process has -100 and -109.5 dBc/Hz phase noises at 1 MHz offset under 4 and 10 mW dc power consumptions, respectively.

A K-band NMOS transformer-feedback VCO is developed by 0.13 μm CMOS technology [3]. The VCO exhibits a 2.2 GHz frequency tuning range. The phase noise at 1 MHz offset is -113 dBc/Hz under 3-mW dc power consumption, and the FOM is -196 dBc/Hz at 23.3 GHz.

The fast growing market in personal wireless communication has motivated the development of fully integrated transceivers using a cost-efficient CMOS process. As one of the most important building blocks provide a programmable carrier frequency for signal transmitting and receiving, the frequency synthesizers have been fabricated in deep-submicron CMOS technologies for applications at multi-gigahertz frequencies. With the limitations imposed on the cut-off frequency of the transistors, it is still a great design challenge to implement CMOS synthesizers operating at frequencies beyond 10 GHz.

For phase-locked loop (PLL)-based frequency synthesizers, the only circuit modules operating at the carrier frequency are the voltage-controlled oscillator (VCO) [1]-[3] and the frequency divider [4]. Therefore, efforts have been made to develop novel CMOS circuit techniques for high-frequency VCOs and dividers. In addition, fully integrated frequency synthesizers operating at microwave and millimeter-wave frequencies have been successfully implemented in a standard CMOS process [5]-[6].