Focus Research



Three-dimensional integrated circuits (3-D ICs) are emerging as an attractive solution to overcome the interconnection bottleneck in nanometer designs. In addition to improving interconnection performance, 3-D ICs also offer various advantages such as higher packaging density, smaller chip area, and heterogeneous integration technologies. However, the electrical properties of through-silicon-vias (TSVs) make signal/power integrity a challenge for 3-D IC designers. In addition, 3-D technology poses another challenge in thermal management due to high power density increasing with the number of vertically stacked device layers.

For the signal/power integrity issues, a novel passive equalizer composed of a parallel resistance–capacitance (RC) circuit is presented. It is capable of compensating the lossy effects of TSVs and achieving nearly zero timing jitter [1]. Another work is to analyze the slow wave effect in TSVs. A conformal mapping method is applied to modify the conventional model, and the improved model matches full-wave simulation results up to 40 GHz [2]. For thermal modeling researches, we presented a fast and accurate thermal-wake aware thermal model for integrated microchannel 3-D ICs. When compared to conventional numerical approaches, our latest results achieves 3300 times speed-up with errors less than 5% [3]. We also demonstrate thermal-aware placements using our thermal model. It shows that the proposed model can be used to reduce peak temperatures, which is considered important for 3-D IC designs.

  • [1] R.-B. Sun, C.-Y. Wen, and R.-B. Wu, “Passive equalizer design for through silicon vias with perfect compensation,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 1, no. 4, pp. 1815-1822, Nov. 2011.
  • [2] T.-Y. Cheng, C.-D. Wang, Y.-P. Chiou, and T.-L. Wu, “Accuracy-improved through-silicon-via model using conformal mapping technique,” 2011 IEEE Conf. Elect. Performance Electron. Packag. Syst., pp. 189-192, Oct. 2011.
  • [3] H. Mizunuma, Y.-C. Lu, and C.-L. Yang, “Thermal modeling and analysis for 3-D ICs with integrated microchannel cooling,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.s, vol. 30, no. 9, pp. 1293-1306, Sep. 2011.